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load delay slot

См. также в других словарях:

  • Delay slot — In computer architecture, a delay slot is an instruction slot that gets executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or… …   Wikipedia

  • Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… …   Wikipedia

  • Reduced instruction set computer — The acronym RISC (pronounced risk ), for reduced instruction set computing, represents a CPU design strategy emphasizing the insight that simplified instructions which do less may still provide for higher performance if this simplicity can be… …   Wikipedia

  • UltraSPARC IIi — Processeur UltraSPARC IIi L UltraSPARC IIi, successeur de l UltraSPARC, est un microprocesseur 64 bits de Sun Microsystems dont la distribution commença en 1997. L UltraSPARC IIi est basé sur les spécifications SPARC version 9, et équipe… …   Wikipédia en Français

  • Liste von Hallo-Welt-Programmen/Programmiersprachen — Dies ist eine Liste von Hallo Welt Programmen für gebräuchliche Programmiersprachen. Weitere Beispiele für grafische Benutzeroberflächen, Web Technologien, exotische Programmiersprachen und Textauszeichnungssprachen sind unter Liste von Hallo… …   Deutsch Wikipedia

  • Branch predictor — In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. This is called branch prediction. Branch predictors are… …   Wikipedia

  • Instruction set — An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception… …   Wikipedia

  • Evans & Sutherland ES-1 — The ES 1 was Evans Sutherland s abortive attempt to enter the supercomputer market. About to be released just as the market was drying up in the post cold war military wind down, only a handful were built and only two sold.Jean Yves Leclerc was a …   Wikipedia

  • Berkeley RISC — was one of two seminal research projects into RISC based microprocessor design taking place under ARPA s VLSI project. RISC was led by David Patterson at the University of California, Berkeley between 1980 and 1984, while the other was taking… …   Wikipedia

  • SPARC — (from Scalable Processor Architecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems.SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to… …   Wikipedia

  • Super Harvard Architecture Single-Chip Computer — The Super Harvard Architecture Single Chip Computer (SHARC) is a high performance floating point and fixed point DSP from Analog Devices,not to be confused with Hitachi s SuperH (SH) microprocessor. SHARC is used in a variety of signal processing …   Wikipedia

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